Method for fabricating semiconductor device

ABSTRACT

In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. patent applicationSer. No. 14/169,608 filed on Jan. 31, 2014; which claims priority underKorean Patent Application No. 10-2013-0067884 filed on Jun. 13, 2013 inthe Korean Intellectual Property Office, and all the benefits accruingtherefrom under 35 U.S.C. 119, the content of which in its entirety isherein incorporated by reference.

BACKGROUND

Embodiments of the present inventive concepts relate to methods forfabricating semiconductor devices.

Semiconductor devices continue development at a rapid pace asinformation media become ever more ubiquitous. In current semiconductorproducts, there is an ever-increasing demand for high integration, alongwith increased quality and reduced cost. In order to achieve highintegration, scaling down of semiconductor devices is needed.

Studies are being performed to meet the demands for increased operationspeed and degree of integration in semiconductor devices. Suchsemiconductor devices includes discrete devices such as MOS transistors.However, along with further integration of semiconductor devices, thesize of a gate of the MOS transistor is gradually reduced and the lowerchannel region of the gate is likewise gradually narrowed.

A critical dimension of the gate region of the transistor largelyaffects electrical properties of the transistor. That is, as thesemiconductor device becomes more highly integrated, when the width ofthe gate region is narrowed, the resulting gap between the source regionand the drain region which are formed with a gate region therebetween isalso narrowed.

SUMMARY

In an aspect, a method for fabricating a semiconductor device comprises:providing a first gate electrode and a second gate electrode on asubstrate, the first gate electrode and the second gate electrode beingformed in a first region and a second region of the substrate,respectively; forming a conductive buffer layer along sidewalls of thefirst gate electrode and the second gate electrode and on upper surfacesof the first gate electrode and second gate electrode; forming a firstmask pattern covering the first region of the substrate on the bufferlayer; and forming a first impurity region in the substrate at sides ofthe second gate electrode using the first mask pattern as a mask of anion implantation process.

In some embodiments, the first mask pattern comprises a bottomanti-reflective coating (BARC).

In some embodiments, the forming of a first mask pattern includes:forming a mask film which covers the first gate electrode and the secondgate electrode on the buffer layer; and removing the mask film whichcovers the second region using a mixture gas including oxygen.

In some embodiments, the mixture gas further includes chlorine.

In some embodiments, a fraction of oxygen in the mixture gas is a firstfraction and a fraction of chlorine in the mixture gas is a secondfraction, and the second fraction is larger than the first fraction.

In some embodiments, the forming of a first mask pattern includes:forming a mask film which covers the first gate electrode and the secondgate electrode on the buffer layer; and removing the mask film whichcovers the second region using mixture gas including nitrogen andhydrogen.

In some embodiments, the buffer layer includes a TiN film or anamorphous silicon film.

In some embodiments, the method further comprises: after forming thebuffer layer and before forming the first mask pattern, forming an upperbuffer layer along the buffer layer, wherein the upper buffer layerincludes at least one of a silicon nitride film and a silicon oxidefilm.

In some embodiments, the method further comprises: before forming thebuffer layer, forming a lower buffer layer along the first gateelectrode and the second gate electrode.

In some embodiments, the forming of a buffer layer includes conformallyforming the buffer layer on the substrate, the first gate electrode, andthe second gate electrode.

In some embodiments, the method further comprises: after removing thefirst mask pattern, forming a second mask pattern which covers thesecond region on the buffer layer; and forming a second impurity regionhaving a different conductive type from that of the first impurityregion, in the substrate at sides of the first gate electrode using thesecond mask pattern as a mask of an ion implantation process.

In some embodiments, the second mask pattern comprises a BARC.

In some embodiments, the method further comprises: sequentially removingthe second mask pattern and the buffer layer to expose the substrate,the first gate electrode, and the second gate electrode.

In some embodiments, the method further comprises: forming a firstsource/drain at sides of the first gate electrode; and forming a secondsource/drain at sides of the second gate electrode.

In some embodiments, the ion implantation process comprises a halo ionimplantation process.

In another aspect, a method for fabricating a semiconductor devicecomprises: forming a first active region and a second active region;forming a gate electrode intersecting the first active region and thesecond active region on the first active region and the second activeregion; conformally forming a conductive buffer layer on the firstactive region, the second active region, and the gate electrode; forminga first mask pattern covering the first active region on the bufferlayer; and performing a halo ion implantation process in the secondactive region at sides of the gate electrode using the first maskpattern.

In some embodiments, the method further comprises: after removing thefirst mask pattern, forming a second mask pattern which covers thesecond active region on the buffer layer; and performing the halo ionimplantation process on the first active region at sides of the gateelectrode using the second mask pattern.

In some embodiments, the first mask pattern is a BARC

In some embodiments, the buffer layer includes a TiN film or anamorphous silicon film.

In some embodiments, the first active region is a region where a pull-uptransistor of an SRAM is formed and the second active region is a regionwhere a pull-down transistor of the SRAM is formed.

In some embodiments, the first active region and the second activeregion are fin type active patterns.

In another aspect, a method for fabricating a semiconductor device,comprises: forming a first fin type active pattern and a second fin typeactive pattern on a substrate, the first fin type active pattern and thesecond fin type active pattern being formed in a first region and asecond region of the substrate, respectively; forming a first dummy gateelectrode intersecting the first fin type active pattern on the firstfin type active pattern and a second dummy gate electrode intersectingthe second fin type active pattern on the second fin type activepattern; forming a buffer layer including a TiN film or amorphoussilicon on the first and second fin type active patterns and the firstand second dummy gate electrodes; forming a first mask pattern coveringthe first region on the buffer layer, the first mask pattern comprisinga BARC; forming a first impurity region in the second fin type activepattern at sides of the second dummy gate electrode using the first maskpattern as a mask of an ion implantation process; after removing thefirst mask pattern, forming a second mask pattern covering the secondregion on the buffer layer, the second mask pattern being a BARC; andforming a second impurity region having a different conductive type fromthe first impurity region, in the first fin type active pattern at sidesof the first dummy gate electrode using the second mask pattern as amask of an ion implantation process.

In some embodiments, the first impurity region and the second impurityregion comprises halo ion implantation regions.

In some embodiments, the method further comprises: sequentially removingthe second mask pattern and the buffer layer; forming a firstsource/drain at sides of the first dummy gate electrode; and forming asecond source/drain at sides of the second dummy gate electrode.

In some embodiments, the method further comprises: forming an interlayerinsulating layer which covers the first and second dummy gate electrodesand the first and second sources/drains, on the substrate; planarizingthe interlayer insulating layer to expose the first dummy gate electrodeand the second dummy gate electrode; removing the first dummy gateelectrode and the second dummy gate electrode to form a first trench anda second trench in the interlayer insulating layer; and forming a firstgate electrode which buries the first trench and a second gate electrodewhich buries the second trench.

In another aspect, a method for fabricating a semiconductor device,comprises: providing a first gate structure and a second gate structureon a substrate, at a first region and a second region of the substrate,respectively; forming a conductive buffer layer along sidewalls of thefirst gate structure and the second gate structure and on upper surfacesof the first gate structure and second gate structure; forming a firstmask pattern covering the first region of the substrate on the bufferlayer; and forming a first impurity region in the substrate at sides ofthe second gate structure using the first mask pattern as a mask of anion implantation process.

In some embodiments, the first gate structure comprises a first gateelectrode and wherein the second gate structure comprises a second gateelectrode.

In some embodiments, the first impurity region is formed followingproviding the first gate electrode and the second gate electrode.

In some embodiments, the conductive buffer layer is present on thesidewalls and upper surfaces of the second gate structure during formingof the first impurity region.

In some embodiments, the first gate structure comprises a first dummygate electrode and wherein the second gate structure comprises a seconddummy gate electrode.

In some embodiments, the method further comprises, following forming thefirst impurity region, replacing the first dummy gate electrode and thesecond dummy gate electrode with first and second gate electrodesrespectively.

In some embodiments, the conductive buffer layer is present on thesidewalls and upper surfaces of the second gate structure during formingof the first impurity region.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventiveconcepts will become more apparent by describing in detail embodimentsthereof with reference to the attached drawings in which:

FIGS. 1 to 11 are diagrams illustrating intermediate processes of amethod for fabricating a semiconductor device according to an embodimentof the present inventive concepts;

FIGS. 12 to 20 are diagrams illustrating intermediate processes of amethod for fabricating a semiconductor device according to anotherembodiment of the present inventive concepts;

FIG. 21 is a diagram illustrating a layout of intermediate processes ofa method for fabricating a semiconductor device according to yet anotherembodiment of the present inventive concepts;

FIGS. 22 and 23 are a circuit diagram and a layout diagram illustratinga semiconductor device which is fabricated using the layout of FIG. 21;

FIG. 24 is a block diagram illustrating an electronic system including asemiconductor device fabricated by the method for fabricating asemiconductor device according to some embodiments of the presentinventive concepts; and

FIGS. 25 and 26 illustrate exemplary semiconductor systems to which asemiconductor device fabricated by the method for fabricating asemiconductor device according to some embodiments of the presentinventive concepts may be applied.

DETAILED DESCRIPTION OF EMBODIMENTS

Advantages and features of the present inventive concepts and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of preferred embodiments and theaccompanying drawings. The present inventive concepts may, however, beembodied in many different forms and should not be construed as beinglimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete andwill fully convey the concepts of the inventive concepts to thoseskilled in the art, and the present inventive concepts will only bedefined by the appended claims. Like reference numerals refer to likeelements throughout the specification.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcepts. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the teinis“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on”, “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present inventive concepts.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper”, and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

Embodiments are described herein with reference to cross-sectionillustrations that are schematic illustrations of idealized embodiments(and intermediate structures). As such, variations from the shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, these embodiments shouldnot be construed as limited to the particular shapes of regionsillustrated herein but are to include deviations in shapes that result,for example, from manufacturing. For example, an implanted regionillustrated as a rectangle will, typically, have rounded or curvedfeatures and/or a gradient of implant concentration at its edges ratherthan a binary change from implanted to non-implanted region. Likewise, aburied region formed by implantation may result in some implantation inthe region between the buried region and the surface through which theimplantation takes place. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to illustratethe actual shape of a region of a device and are not intended to limitthe scope of the present inventive concepts.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present inventive conceptsbelong. It will be further understood that terms, such as those definedin commonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand this specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Hereinafter, a method of fabricating a semiconductor device according toan embodiment of the present inventive concepts will be described withreference to FIGS. 1 to 11.

FIGS. 1 to 11 are diagrams illustrating intermediate processes of amethod for fabricating a semiconductor device according to an embodimentof the present inventive concepts.

Referring to FIG. 1, a substrate 100 including a first region I and asecond region II is provided. The first region I and the second regionII may be separated from each other, for example by an isolation region,or connected to each other.

The first region I and the second region II may include an active regionin which a gate of a transistor is formed. In FIG. 1, for theconvenience of description, an isolation layer is not illustrated butonly an active region is illustrated.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, the first region I may bea PMOS region and a second region II may be an NMOS region. For example,in the first region I, a pull up transistor of an SRAM may be formed andin the second region II, a pull down transistor or a pass transistor ofthe SRAM may be formed.

In various embodiments, the substrate 100 may comprise a bulk silicon ora silicon-on-insulator (SOI). Alternatively, the substrate 100 maycomprise a silicon substrate or may optionally include other materials,for example, germanium, silicon germanium, indium antimonide, a leadtelluride compound, indium arsenide, indium phosphide, gallium arsenide,or gallium antimonide. However, embodiments are not limited thereto, andany of a number of suitable substrate materials are equally applicableto the present inventive concepts.

In the first region I on the substrate 100, a first gate dielectric film110 and a first gate electrode 120 are formed. In the second region IIon the substrate 100, a second gate dielectric film 210 and a secondgate electrode 220 are formed. Even though not illustrated, gate hardmasks may be further formed on the first gate electrode 120 and thesecond gate electrode 220, respectively.

The first gate dielectric film 110 and a second gate dielectric film 210may comprise, for example, a silicon oxide film, SiON, GexOyNz,GexSiyOz, a dielectric film having a high dielectric constant, acombination thereof, or a lamination layer in which the above-mentionedlayers are sequentially laminated. The dielectric film having a highdielectric constant may include at least one of hafnium oxide, hafniumsilicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconiumoxide, zirconium silicon oxide, tantalum oxide, titanium oxide, bariumstrontium titanium oxide, barium titanium oxide, strontium titaniumoxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, andlead zinc niobate, but is not limited thereto. The first gate dielectricfilm 110 and the second gate dielectric film 210 may be formed using,for example, thermal treatment, chemical treatment, an atomic layerdeposition (ALD) method, or a chemical vapor deposition (CVD) method, orother suitable formation method. When the first gate dielectric film 110and the second gate dielectric film 210 include a dielectric substancehaving a high dielectric constant, a barrier layer may be further formedbetween the first gate dielectric film 110 and the first gate electrode120 and/or the second gate dielectric film 210 and the second gateelectrode 220. The barrier layer may include at least one of titaniumnitride (TiN), tantalum nitride (TaN), and a combination thereof.

The first gate electrode 120 and the second gate electrode 220 may besilicon and specifically, and may include one of poly silicon (poly Si),amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN),tantalum nitride (TaN), aluminum (Al), tungsten (W), and a combinationthereof. The poly silicon may be formed using a chemical vapordeposition method and the amorphous silicon may be formed using asputtering method, a chemical vapor deposition method, or a plasmadeposition method, but is not limited thereto, as other suitable methodsare equally applicable to the present inventive concepts.

Referring to FIG. 2, on the substrate 100, a lower buffer layer 12, abuffer layer 10, and an upper buffer layer 15 are sequentially formed.Specifically, the lower buffer layer 12, the buffer layer 10, and theupper buffer layer 15 are sequentially formed along sidewalls of thefirst gate electrode 120 and the second gate electrode 220 and on uppersurfaces of the first gate electrode 120 and the second gate electrode220.

In some embodiments, the lower buffer layer 12, the buffer layer 10, andthe upper buffer layer 15 may be conformally formed on the substrate100, the first gate electrode 120, and the second gate electrode 220,respectively.

Specifically, in some embodiments, the lower buffer layer 12 is formedalong upper and sidewall surfaces of the first gate electrode 120 andthe second gate electrode 220 on the substrate 100. In some embodiments,the lower buffer layer 12 may include silicon nitride and be formedusing a chemical vapor deposition method or an atomic layer depositionmethod, or other suitable formation method.

The buffer layer 10 is formed along the lower buffer layer 12. In someembodiments, the buffer layer 10 may include a conductive material, andfor example, a TiN layer or an amorphous silicon layer. The buffer layer10 may be formed using the chemical vapor deposition method or theatomic layer deposition method. A thickness of the buffer layer 10 isfor example, 30 Å or larger and 200 Å or smaller. In a subsequentprocess, the buffer layer 10 may serve as an etch stop layer and/or abuffer of an ion implantation process.

The upper buffer layer 15 is formed along the buffer layer 12. The upperbuffer layer 15 may include at least one of a silicon nitride film and asilicon oxide film and may be formed using the chemical vapor depositionmethod or the atomic layer deposition method. A thickness of the upperbuffer layer 15 is for example, 30 Å or larger and 100 Å or smaller. Ina subsequent process, the upper buffer layer 15 may serve as an etchstop layer and/or a buffer of an ion implantation process, together withthe buffer layer 10.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, it is described that thebuffer layer 10 and the upper buffer layer 15 are formed together, butthe inventive concepts are not limited thereto. That is, in someembodiments, the buffer layer 10 is formed on the lower buffer layer 12,and the upper buffer layer 15 is not formed on the buffer layer 10.

Referring to FIG. 3, a first mask film 22 which covers the first gateelectrode 120 and the second gate electrode 220 are formed on the bufferlayer 10. Specifically, the first mask film 22 which is formed on thebuffer layer 10 is formed so as to be in contact with the upper bufferlayer 15.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, the first mask film 22may comprise a BARC (bottom anti-reflective coating) film.

Next, a photosensitive film pattern 30 is formed on the first mask film11. The first photosensitive film pattern 30 exposes the first mask film22 which is formed on the second gate electrode 220 but covers the firstmask film 22 which is formed on the first gate electrode 120.

In other words, the first photosensitive film pattern 30 is formed onthe first region I to expose the second region II. Further, the firstphotosensitive film pattern 30 overlaps the first gate electrode 120 butdoes not overlap the second gate electrode 220.

Referring to FIG. 4, the first photosensitive film pattern 30 is used asa mask of a first etching process to remove the first mask film 22 whichis formed in the second region II. That is, by the first etching process40, a first mask pattern 20 which covers the first region I of thesubstrate 100 is formed on the buffer layer 10. In some embodiments, thefirst mask pattern 20 which is formed in the first region I is the BARCpattern.

In other words, the first mask film 22 which covers the second region IIis removed by the first etching process 40 to form the first maskpattern 20. The upper buffer layer 15 is exposed by the first maskpattern 20. The first mask pattern 20 is formed by the first etchingprocess 40 so that the upper buffer layer 15 may serve as an etch stoplayer for the first etching process 40 in the second region II.

In some embodiments, the first mask pattern 20 and the firstphotosensitive film pattern 30 which are formed in the first region Iform a lamination layer to be used as a mask in the first ionimplantation process 50 which will be performed later.

In some embodiments, the first etching process 40 which removes thefirst mask film 22 which covers the second region II may be a dryetching process and for example, a reactive ion etching (RIE) process.

As an example of the dry etching used to form the first mask pattern 20,a mixture gas including oxygen is used as an etching gas to etch andremove the first mask film 22 which covers the second region II. In someembodiments, the mixture gas which is used as the etching gas mayinclude chlorine in addition to oxygen. Further, the mixture gas mayfurther include helium, or another suitable element or compound.

In the mixture gas which is used in the etching process, a fraction ofoxygen is a first fraction, a fraction of chlorine is a second fraction,and a fraction of helium is a third fraction. In some embodiments of themethod for fabricating a semiconductor device according to theembodiments of the present inventive concepts, in the mixture gas, thesecond fraction of chlorine may be larger than the first fraction ofoxygen. For example, in the mixture gas, a ratio of the second fractionof chlorine with respect to the first fraction of oxygen may be a valuebetween 1.1 and 7.

Further, in other embodiments, in the mixture gas, the third fraction ofhelium may be larger than the first fraction of oxygen and the secondfraction of chlorine. In addition, in the mixture gas, an amount ofhelium may be larger than a total amount of oxygen and chlorine.

When the first mask film 22 which covers the second region II is removedby the reactive ion etching process, a bias may be applied to thesubstrate 100. For example, the bias which is applied to the substrate100 may be between 10 V and 3000 V, but is not limited thereto. Further,in the reactive ion etching process, a power which generates plasma maybe between 50 W and 600 W, but is not limited thereto.

As another example of the dry etching used to form the first maskpattern 20, mixture gas including nitrogen and hydrogen is used as theetching gas to etch and remove the first mask film 22 which covers thesecond region II.

Referring to FIG. 5, the first mask pattern 20 is used as a mask of thefirst ion implantation process 50 to form a second impurity region 230at side regions of the second gate electrode 220. The second impurityregion 230 is formed in the substrate 100 of the second region II.Specifically, the mask pattern 20 and the first photosensitive filmpattern 30 may be used as a mask of the first ion implantation process50.

The impurity which is injected by the first ion implantation process 50passes through the upper buffer layer 15 the buffer layer 10, and thelower buffer layer 12 to be injected into the substrate 100.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, the first ionimplantation process 50 may be a halo ion implantation process whichinjects the impurity into the substrate 100 at a predetermined angle,but is not limited thereto. That is, the first ion implantation process50 may be an ion implantation process which injects the impurity to besubstantially perpendicular to the substrate 100. In FIG. 5, a secondimpurity region 230 is illustrated as a halo ion region, but is notlimited thereto. Therefore, the second impurity region 230 may beconfigured as a lightly doped impurity extension region.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, when the first ionimplantation process 50 is the halo ion implantation process, the secondregion II may be a region in which the NMOS is formed so that the secondimpurity region 230 may be a region including a p-type impurity.

However, when the first ion implantation process 50 is an ionimplantation process which forms the lightly doped impurity extensionregion, the second impurity region 230 may be a region including an ntype impurity.

Referring to FIG. 6, in some embodiments, the first mask pattern 20 andthe first photosensitive film pattern 30 which are formed in the firstregion I are removed to expose the upper buffer layer 15.

For example, gas including hydrogen H₂ and nitrogen N₂ is used to ashand strip the first mask pattern 20 and the first photosensitive filmpattern 30.

Next, a second mask film 27 is formed on the buffer layer 10 to coverthe first gate electrode 120 and the second gate electrode 220.Specifically, the second mask film 27 which is formed on the bufferlayer 10 is formed to be in contact with the upper buffer layer 15.

In some embodiments of the method for fabricating a semiconductor deviceaccording to the embodiments of the present inventive concepts, thesecond mask film 27 may comprise a bottom anti-reflective coating (BARC)film which is the same as the first mask film 22 of FIG. 3.

Next, a second photosensitive film pattern 35 is formed on the secondmask film 27. The second photosensitive film pattern 35 exposes thesecond mask film 27 which is formed on the first gate electrode 120 butcovers the second mask film 27 formed on the second gate electrode 220.That is, the second photosensitive film pattern 35 is formed on thesecond region II to expose the first region I.

Referring to FIG. 7, the second photosensitive film pattern 35 is usedas a mask of a second etching process 45 to remove the second mask film27 formed in the first region I. That is, through the second etchingprocess 45, the second mask pattern 25 which covers the second region IIof the substrate 100 is formed on the buffer layer 10. In someembodiments, the second mask pattern 25 which is formed in the secondregion II comprises a BARC pattern.

The second mask film 27 which covers the first region I is removed bythe second etching process 45 so that the second mask pattern 25 isformed. The upper buffer layer 15 is exposed by the second mask pattern25. The second mask pattern 25 is formed by the second etching process45 so that the upper buffer layer 15 may serve as an etch stop layer forthe second etching process 45.

In some embodiments, the second mask pattern 25 and the secondphotosensitive film pattern 35 which are formed in the second region IIform a lamination layer to be used as a mask in the second ionimplantation process 55 which will be performed later.

In some embodiments, the second etching process 45 which forms thesecond mask pattern 25 is performed in a condition and a method whichare substantially same as the first etching process 40 which has beendescribed with reference to FIG. 4. Accordingly, a repeated descriptionof the second etching process 45 will be omitted.

Referring to FIG. 8, the second mask pattern 25 and the secondphotosensitive film pattern 35 are used as a mask of a second ionimplantation process 55 to form the first impurity region 130 at bothsides of the first gate electrode 120. The first impurity region 130 isformed in the substrate 100 in the first region I. In some embodiments,the first impurity region 130 may be an impurity region which has adifferent conductive type from that of the second impurity region 230.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, the second ionimplantation process 55 may be a halo ion implantation process whichinjects the impurity into the substrate 100 at a predetermined angle,but is not limited thereto. That is, the first impurity region 130 isillustrated as a halo ion region in FIG. 8; however, embodiments are notlimited thereto. Therefore, the first impurity region 130 may be alightly doped impurity extension region, or other type of impurityregion.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, when the second ionimplantation process 55 is the halo ion implantation process, the firstregion I may be a region in which the PMOS is formed so that the firstimpurity region 130 may be a region including an n-type impurity.

However, when the second ion implantation process 55 is an ionimplantation process which forms the lightly doped impurity extensionregion, the first impurity region 130 may be a region including a p-typeimpurity

Referring to FIG. 9, the second mask pattern 25 and the secondphotosensitive film pattern 35 which are formed in the second region IIare removed to expose the upper buffer layer 15. For example, in someembodiments, a gas including hydrogen (H₂) and nitrogen (N₂) is used toash and strip the second mask pattern 25 and the second photosensitivefilm pattern 35.

Next, the upper buffer layer 15, the buffer layer 10, and the lowerbuffer layer 12 are sequentially removed to expose the first gateelectrode 120, the second gate electrode 220, and the substrate 100.

Specifically, in some embodiments, the upper buffer layer 15 may beremoved using a wet etching process. When the upper buffer layer 15includes a silicon oxide film, the upper buffer layer 15 may be removedusing a hydrofluoric acid solution. When the upper buffer layer 15includes a silicon nitride film, the upper buffer layer 15 may beremoved using a phosphoric acid solution.

In some embodiments, the buffer layer 10 may be removed using a wetetching process. When the buffer layer 10 includes a TiN film, thebuffer layer 10 may be removed using a hydrogen peroxide solution. Whenthe buffer layer 10 includes an amorphous silicon film, the buffer layer10 may be removed using an ammonium hydroxide or tetralkyl ammoniumhydroxide solution, for example, a tetramethyl ammonium hydroxide (TMAH)solution.

Referring to FIG. 10, a first gate spacer 140 is formed on a side of thefirst gate electrode 120 and a second gate spacer 240 is formed on aside of the second gate electrode 220.

Specifically, the spacer film is conformally formed on the substrate100, the first gate electrode 120, and the second gate electrode 220.The spacer film is etched using an anisotropic dry etching process, sothat the first gate spacer 140 and the second gate spacer 240 are formedon sides of the first gate electrode 120 and the second gate electrode220, respectively. The first gate spacer 140 and the second gate spacer240 may include a silicon nitride film, a silicon oxynitride film, asilicon oxide film, and a combination thereof.

Referring to FIG. 11, a first source/drain 150 is formed at sides of thefirst gate electrode 120 and a second source/drain 250 is formed atsides of the second gate electrode 220.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, the PMOS may be formed inthe first region I so that the first source/drain 150 may include acompressive stress material having a lattice constant which is largerthan that of the substrate 100. For example, when the substrate 100 is asilicon substrate, the compressive stress material may be silicongermanium (SiGe) which has a lattice constant larger than that ofsilicon. The compressive stress material applies a compressive stress tothe first source/drain 150 to improve a mobility of a carrier of achannel region.

In the method for fabricating a semiconductor device according to theembodiments of the present inventive concepts, the NMOS may be formed inthe second region II so that the second source/drain 150 may include thesame material as the substrate 100 or a tensile stress material. Forexample, when the substrate 100 is a silicon substrate, the secondsource/drain 250 may be Si or a material having a lattice constantsmaller than that of Si (for example, SiC).

It is described herein that, in the method for fabricating asemiconductor device according to the embodiment of the presentinventive concepts, the source/drains 150 and 250 are formed afterforming the gate electrodes 120 and 220, but embodiments of the presentinventive concepts are not limited thereto. For example, in someembodiments, the source/drain regions can be formed prior to forming thegate electrodes and/or after forming the gate electrodes.

The fabricating method in which a gate electrode is formed after formingthe source/drain will be described with reference to FIGS. 12 to 20.

A method for fabricating a semiconductor device according to anotherembodiment of the present inventive concepts will be described withreference to FIGS. 3 to 8 and 12 to 20.

FIGS. 12 to 20 are diagrams illustrating intermediate processes of amethod for fabricating a semiconductor device according to anotherembodiment of the present inventive concepts, in which FIG. 14 is across-sectional view taken long lines A-A and B-B of FIG. 13.

Referring to FIG. 12, a first fin type active pattern 300 and a secondfin type active pattern 400 are formed on the substrate 100. In someembodiments, the first fin type active pattern 300 is formed in thefirst region I and the second fin type active pattern 400 is formed inthe second region II.

The first fin type active pattern 300 and the second fin type activepattern 400 may extend in an elongated fashion along second directionsY1 and Y2. The first fin type active pattern 300 and the second fin typeactive pattern 400 may be a part of the substrate 100 and may include anepitaxial layer which is grown from the substrate 100. In someembodiments, the isolation layer 60 may cover side portions of the fintype active pattern 300 and the second fin type active pattern 400.

In some embodiments, the fin type active pattern 300 and the second fintype active pattern 400 may include silicon or germanium which is anelemental semiconductor material. Further, in other embodiments, thefirst fin type active pattern 300 and the second fin type active pattern400 may include a compound semiconductor and for example, a IV-IVcompound semiconductor or a III-V compound semiconductor. Specifically,as an example of the IV-IV compound semiconductor, the first fin typeactive pattern 300 and the second fin type active pattern 400 may be abinary compound or ternary compound including at least two of carbon(C), silicon (Si), germanium (Ge), and tin (Sn) or a compound in which aIV element is doped in the above compound. As an example of the III-Vcompound semiconductor, the first fin type active pattern 300 and thesecond fin type active pattern 400 may be one of a binary compound, aternary compound, and a quaternary compound in which at least one of IIIelements such as aluminum (Al), gallium (Ga), and indium (In) is coupledto one of V elements such as phosphorous (P), arsenic (As), andantimonium (Sb).

Referring to FIGS. 13 and 14, the etching process is performed using afirst hard mask pattern 323 and a second hard mask pattern 423 to form afirst dummy gate electrode 321 which extends in a first direction X1 soas to intersect the first fin type active pattern 300 and a second dummygate electrode 421 which extends in a first direction X2 so as tointersect the second fin type active pattern 400.

A first dummy gate dielectric film 311 may be formed between the firstfin type active pattern 300 and the first dummy gate electrode 321 and asecond dummy gate dielectric film 421 may be formed between the secondfin type active pattern 400 and the second dummy gate electrode 421.

The first dummy gate dielectric film 311 and the second dummy gatedielectric film 411 may include one of a silicon oxide film (SiO₂), asilicon oxynitride film (SiON), and a combination thereof. The firstdummy gate electrode 321 and the second dummy gate electrode 421 mayinclude one of poly silicon (poly Si), amorphous silicon (a-Si), and acombination thereof.

In the method for fabricating a semiconductor device according toanother embodiment of the present inventive concepts, even though it isdescribed that the first dummy gate dielectric film 311 and the seconddummy gate dielectric film 411 are formed, the inventive concepts arenot limited thereto. In other words, the first dummy gate dielectricfilm 311 and the second dummy gate dielectric film 411 are notre-deposited in a fabricating process which will be described withreference to FIG. 20, but instead a third gate dielectric film 310 and afourth gate dielectric film 410 including an interfacial layer and amaterial having a high dielectric constant may be formed, respectively.

Further, in the method for fabricating a semiconductor device accordingto another embodiment of the present inventive concepts, even though itis described that the first dummy gate electrode 321 and the seconddummy gate electrode 421 are formed on the fin type active patterns 300and 400, the inventive concepts are not limited thereto. In other words,the first dummy gate electrode 321 and the second dummy gate electrode421 may be formed on a top surface of an active region which isdisplaced on the same plane as a top surface of the substrate 100 asillustrated in FIG. 1.

Subsequent processes will be described with reference to FIG. 14 whichis a cross-sectional view taken along lines A-A and B-B of FIG. 13 andrelated FIGS. 15-20.

Referring to FIG. 15, the lower buffer layer 12, the buffer layer 10,and the upper buffer layer 15 are sequentially formed on the first fintype active pattern 300 and the second fin type active pattern 400.Specifically, the lower buffer layer 12, the buffer layer 10, and theupper buffer layer 15 are sequentially formed on upper surfaces of thefirst dummy gate electrode 321 and the second dummy gate electrode 421and formed along sidewall surfaces of the first dummy gate electrode 321and the second dummy gate electrode 421. In some embodiments, the lowerbuffer layer 12, the buffer layer 10, and the upper buffer layer 15 mayalso be formed on the isolation layer 60 of FIG. 13.

The lower buffer layer 12, the buffer layer 10, and the upper bufferlayer 15 may be conformally formed on the first fin type active pattern300, the second fin type active pattern 400, the first gate electrode120, and the second gate electrode 220.

The lower buffer layer 12, the buffer layer 10, and the upper bufferlayer 15 in the present embodiment, can be the same as that describedabove in connection with the embodiment of FIG. 2, and thus a repeateddescription thereof will be omitted.

Referring to FIG. 16, by the fabricating process which has beendescribed with reference to FIGS. 3 to 8, a third impurity region 330 isformed at sides of the first dummy gate electrode 321 and a fourthimpurity region 430 is formed at sides of the second dummy gateelectrode 421. The third impurity region 330 and the fourth impurityregion 440 are forming in the first fin type active pattern 300 and thesecond fin type active pattern 400, respectively.

In some embodiments, the third impurity region 330 and the fourthimpurity region 440 may be a halo ion injection region, but are notlimited thereto. In some embodiments, the third impurity region 330 mayhave a different conductive type from that of the fourth impurity region430.

Referring to FIGS. 8 and 16, the second mask pattern 25 and the secondphotosensitive film pattern 35 which are formed in the second region IIare removed to expose the upper buffer layer 15.

Next, the upper buffer layer 15, the buffer layer 10, and the lowerbuffer layer 12 are sequentially removed to expose the first dummy gateelectrode 321, the second dummy gate electrode 421, the first fin typeactive pattern 300, and the second fin type active pattern 400.

Referring to FIG. 17, a third gate spacer 340 is formed at a side of thefirst dummy gate electrode 321 and a fourth gate spacer 440 is formed ata side of the second dummy gate electrode 421.

In some embodiments, the third gate spacer 340 and the fourth gatespacer 440 may include a silicon nitride film, a silicon oxynitridefilm, a silicon oxide film, and a combination thereof, or other suitablematerials.

When the third gate spacer 340 and the fourth gate spacer 440 areformed, a first recess 355 and a second recess 455 may be formed in thefirst fin type active pattern 300 and the second fin type active pattern400, respectively, but is not limited thereto.

Next, a third source/drain 350 is formed at both sides of the firstdummy gate electrode 321 and a fourth source/drain 450 is formed at bothsides of the second dummy gate electrode 421. The third source/drain 350is formed in the first recess 355 and formed on the first fin typeactive pattern 300. The fourth source/drain 450 is formed in the secondrecess 455 and formed on the second fin type active pattern 400.

In some embodiments, the first region I may be a region where the PMOSis formed so that the third source/drain 350 may include a compressivestress material having a larger lattice constant than that of thesubstrate 100 and the second region II may be a region where the NMOS isformed so that the fourth source/drain 450 may include the same materialas the substrate 100 or a tensile stress material.

Referring to FIG. 18, an interlayer insulating layer 70 which covers thefirst dummy gate electrode 321, the second dummy gate electrode 421, thethird source/drain 350, and the fourth source/drain 450 is formed on thesubstrate 100.

The interlayer insulating layer 150 may include at least one of amaterial having a low dielectric constant, an oxide film, a nitridefilm, and an oxynitride film. Examples of the material having a lowdielectric constant may include flowable oxide (FOX), tonen silazene(TOSZ), undoped silica glass (USG), borosilica glass (BSG),phosphosilaca glass (PSG), borophosphosilica glass (BPSG), plasmaenhanced tetra ethyl ortho silicate (PRTEOS), fluoride silicate glass(FSG), high density plasma (HDP), plasma enhanced oxide (PEOX), andflowable CVD (FCVD) and a combination thereof, but are not limitedthereto, as other suitable materials may equally apply.

Next, the interlayer insulating layer 70 is planarized until the topsurfaces of the first dummy gate electrode 321 and the second dummy gateelectrode 421 are exposed. For example, the planarizing process may usea chemical mechanical polishing (CMP) process

As a result, the first hard mask pattern 323 and the second hard maskpattern 423 are removed and the top surface of the first dummy gateelectrode 321 and the top surface of the second dummy gate electrode 421are exposed.

Referring to FIG. 19, the first dummy gate electrode 321 and the seconddummy gate electrode 421 are removed. After removing the first dummygate electrode 321 and the second dummy gate electrode 421, the firstdummy gate dielectric film 311 and the second dummy gate dielectric film411 are removed to form a first trench 345 and a second trench 445. Insome embodiments, the top surface of the first fin type active pattern300 and the top surface of the second fin type active pattern 400 areexposed by the first trench 345 and the second trench 445.

In other words, the interlayer insulating layer 70 which includes thefirst trench 345 and the second trench 445 is on the substrate 100. Thefirst trench 345 is formed in the first region I and the second trench445 is formed in the second region II.

In various embodiments, the first dummy gate electrode 321 and thesecond dummy gate electrode 421 may be removed using a wet process or adry process. In the wet etching process, in some embodiments, the firstdummy gate electrode 321 and the second dummy gate electrode 421 areexposed to an aqueous solution containing a hydroxide source for asufficient time at a sufficient temperature so that the first dummy gateelectrode 321 and the second dummy gate electrode 421 may besubstantially removed. In some embodiments, the hydroxide source mayinclude ammonium hydroxide or tetraalkyl ammonium hydroxide, ortetramethyl ammonium hydroxide (TMAH), but is not limited thereto, asother materials are equally applicable.

The first dummy gate dielectric film 311 and the second dummy gatedielectric film 411 may be removed by the wet etching method, the dryetching method, and a combination thereof. The etching solution or theetching gas may vary depending on the material of the first dummy gatedielectric film 311 and the second dummy gate dielectric film 411.

Referring to FIG. 20, a third gate electrode 320 in which the firsttrench 345 is buried and a fourth gate electrode 420 in which the secondtrench 445 is buried are formed. Specifically, the third gate dielectricfilm 310 and the third gate electrode 320 are formed in the first trench345. The fourth gate dielectric film 410 and the fourth gate dielectricfilm 410 are formed in the second trench 445.

The third gate dielectric film 310 and the fourth gate dielectric film410 may include a high dielectric material having a dielectric constantwhich is higher than that of the silicon oxide film. The third gatedielectric film 310 is conformally formed along the side and the bottomsurfaces of the first trench 345 and the fourth gate dielectric film 410is conformally formed along the side and the bottom surfaces of thesecond trench 445.

In some embodiments, the third gate electrode 320 may include a firstmetal layer MG1 and a second metal layer MG2 and the fourth gateelectrode 420 may include a third metal layer MG3 and a fourth metallayer MG4. As illustrated in the drawing, the third gate electrode 320and the fourth gate electrode 420 may be formed by laminating two ormore metal layers, respectively. The first metal layer MG1 and the thirdmetal layer MG3 control a work function and the second metal layer MG2and the fourth metal layer MG4 serve to fill spaces formed by the firstmetal layer MG1 and the third metal layer MG3. For example, the firstmetal layer MG1 and the third metal layer MG3 may include, in someembodiments, at least one of TiN, TaN, TiC, TaC, TiAlC, and TiAl.Further, the second metal layer MG2 and the fourth metal layer MG4 mayinclude W or Al. In other embodiments, he third gate electrode 320 andthe fourth gate electrode 420 may be formed of Si or SiGe, instead ofthe metal.

Referring to FIGS. 1 to 21, a method for fabricating a semiconductordevice according to another embodiment of the present inventive conceptswill be described.

FIG. 21 is a layout diagram of an intermediate process illustrating amethod for fabricating a semiconductor device according to anotherembodiment of the present inventive concepts.

Referring to FIG. 21, a first active region 520 and a second activeregion 510 which are adjacent to each other are formed. The first activeregion 520 is formed in the first region I and the second active region510 is formed in the second region II. The first active region 520 andthe second active region 510 are formed to be elongated in one direction(a vertical direction of FIG. 21).

A gate electrode 505 is formed on the first active region 520 and thesecond active region 510 to intersect the first active region 520 andthe second active region 510. The gate electrode 505 is formed to beelongated in other direction (a horizontal direction of FIG. 21). Thegate electrode 505 is formed to extend over the first region I and thesecond region II.

First, the cross-sectional view taken along lines C-C and D-D of FIG. 21may correspond to FIG. 1. That is, the first active region 520 and thesecond active region 510 are active regions which are defined in thesubstrate 100 so that a top surface of the first active region 520 and atop surface of the second active region 510 may be disposed on the sameplane as the top surface of the substrate 10. In this case, in the gateelectrode 505 which intersects the first active region 520 and thesecond active region 510, the gate electrode 505 which is formed in thefirst region I corresponds to the first gate electrode 120 of FIG. 1 andthe gate electrode 505 which is formed in the second region IIcorresponds to the second gate electrode 120 of FIG. 1.

Alternatively, the cross-sectional view taken along lines C-C and D-D ofFIG. 21 may correspond to FIG. 14. That is, the first active region 520and the second active region 510 may correspond to the first fin typeactive pattern 300 and the second fin type active pattern 400,respectively. In this case, in the gate electrode 505 which intersectsthe first active region 520 and the second active region 510, the gateelectrode 505 which is formed in the first region I corresponds to thefirst dummy gate electrode 321 of FIG. 14 and the gate electrode 505which is formed in the second region II corresponds to the second dummygate electrode 421 of FIG. 14.

Next, by the fabricating processes of FIGS. 2 to 11 or the fabricatingprocesses of FIGS. 15 to 20, impurity regions may be formed in the firstactive region 520 and the second active region 510 which are placed atsides of the gate electrode 505.

FIGS. 22 and 23 are a circuit diagram and a layout diagram illustratinga semiconductor device which is fabricated using the layout of FIG. 21;

Referring to FIGS. 22 and 23, a semiconductor device fabricated usinganother embodiment of the present inventive concepts may include a pairof inverters INV1 and INV2 which are connected in parallel between apower node Vcc and a ground node Vss, and a first pass transistor PS1and a second pass transistor PS2 which are connected to output nodes ofthe inverters INV1 and INV2, respectively. The first pass transistor PS1and the second pass transistor PS2 may be connected to a bit line BL anda complementary bit line BL/, respectively. Gates of the first passtransistor PS1 and the second pass transistor PS2 may be connected to aword line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and afirst pull-down transistor PD1 which are connected in series and thesecond inverter INV2 includes a second pull-up transistor PU2 and asecond pull-down transistor PD2 which are connected in series. The firstpull-up transistor PU1 and the second pull-up transistor PU2 may be PMOStransistors and the first pull-down transistor PD1 and the secondpull-down transistor PD2 may be NMOS transistors.

In order to configure one latch circuit, the first inverter INV1 and thesecond inverter INV2 may be configured such that an input node of thefirst inverter INV1 is connected to an output node of the secondinverter INV2 and an input node of the second inverter INV2 is connectedto an output node of the first inverter INV1.

Here, referring to FIGS. 22 and 23, the first active region 520, thesecond active region 510, the third active region 530, and the fourthactive region 540 which are separated from each other are formed to beelongated in one direction (for example, a vertical direction of FIG.23). Elongated lengths of the first active region 520 and the thirdactive region 530 may be shorter than those of the second active region510 and the fourth active region 540.

Further, a fifth gate electrode 551, a sixth gate electrode 552, aseventh gate electrode 553, and an eight gate electrode 554 areelongated in other direction (for example, a horizontal direction ofFIG. 23) and formed so as to intersect the first active region 520 tofourth active region 540. Specifically, the fifth gate electrode 551completely intersects the first active region 520 and the second activeregion 510 and partially overlaps an end of the third active region 530.The seventh gate electrode 553 completely intersects the fourth activeregion 540 and the third active region 530 and partially overlaps an endof the first active region 520. The sixth gate electrode 552 and theeight gate electrode 554 are formed to intersect the second activeregion 510 and the fourth active region 540, respectively.

As illustrated in the drawings, the first pull-up transistor PU1 isdefined around a region where the fifth gate electrode 551 intersectsthe first active region 520, the first pull-down transistor PD1 isdefined around a region where the fifth gate electrode 551 intersectsthe second active region 510, and the first pass transistor PS1 isdefined around a region where the sixth gate electrode 552 and thesecond active region 510 intersect each other. The second pull-uptransistor PU2 is defined around a region where the seventh gateelectrode 553 intersects the third active region 530, the secondpull-down transistor PD2 is defined around a region where the seventhgate electrode 553 intersects the fourth active region 540, and thesecond pass transistor PS2 is defined around a region where the eighthgate electrode 554 and the fourth active region 540 intersect eachother.

Even though not clearly illustrated, a source/drain may be formed atboth sides of a region where the fifth to eighth gate electrodes 351 to354 intersect the first to fourth active regions 520, 510, 530, and 540.

Further, a plurality of contacts 550 may be formed.

A shared contact 561 simultaneously connects the first active region520, the seventh gate line 553 with a wiring line 571. A shared contact562 simultaneously connects the third active region 530, the fifth gateline 551 with a wiring line 572.

For example, the first pull-up transistor PU1 and the second pull-uptransistor PU2 may have a configuration of a transistor described in thefirst region I of FIGS. 11 and 20, and the first pull-down transistorPD1, the first pass transistor PS1, the second pull-down transistor PD2,and the second pass transistor PS2 may have a configuration of atransistor formed in the second region II of FIGS. 11 and 20.

FIG. 24 is a block diagram illustrating an electronic system including asemiconductor device fabricated by the method for fabricating asemiconductor device according to some embodiments of the presentinventive concepts.

Referring to FIG. 24, an electronic system 1100 according to embodimentsof the present inventive concepts may include a controller 1110, aninput/output device (I/O) 1120, a memory device 1130, an interface 1140,and a bus 1150. The controller 1110, the input/output device 1120, thememory device 1130, and/or the interface 1140 may be connected to eachother through the bus 1150. The bus 1150 corresponds to a path throughwhich data moves.

The controller 1110 may include at least one of a microprocessor, adigital signal processor, a micro controller, and logical elements whichperform a similar function to the above-mentioned devices. Theinput/output device 1120 may include a keypad, a keyboard, and a displaydevice. The memory device 1130 may store data and/or a command language.The interface 1140 may perform a function which transmits data to acommunication network or receives data from the communication network.The interface 1140 may be a wired or wireless type. For example, theinterface 1140 may include an antenna or a wired or wirelesstransceiver. Even though not illustrated in the drawing, the electronicsystem 1100 may further include a high speed DRAM and/or SRAM as anoperation memory for improving an operation of the controller 1110. Thesemiconductor device according to the embodiments of the presentinventive concepts may be provided in the memory device 1130 or providedas a part of the controller 1110 or the input/output device (I/O) 1120.

The electronic system 1100 may be applied to a personal digitalassistant (PDA), a portable computer, a web tablet, a wireless phone, amobile phone, a digital music player, a memory card or other types ofelectronic products which may transmit and/or receive information in awireless communication environment.

FIGS. 25 and 26 illustrate exemplary semiconductor system to which asemiconductor device fabricated by the method for fabricating asemiconductor device according to some embodiments of the presentinventive concepts may be applied.

FIG. 25 illustrates a tablet PC and FIG. 26 illustrates a notebookcomputer. At least one of semiconductor devices which are fabricatedaccording to the embodiments of the present inventive concepts may beused in the tablet PC or the notebook computer. It is apparent to thoseskilled in the art that the semiconductor devices according to theembodiments of the present inventive concepts may be applied to otherintegrated circuit devices which are not illustrated.

The foregoing is illustrative of the present inventive concepts and isnot to be construed as limiting thereof. Although a few embodiments ofthe present inventive concepts have been described, those skilled in theart will readily appreciate that many modifications are possible in theembodiments without materially departing from the novel teachings andadvantages of the present inventive concepts. Accordingly, all suchmodifications are intended to be included within the scope of thepresent inventive concepts as defined in the claims. Therefore, it is tobe understood that the foregoing is illustrative of the presentinventive concepts and is not to be construed as limited to the specificembodiments disclosed, and that modifications to the disclosedembodiments, as well as other embodiments, are intended to be includedwithin the scope of the appended claims. The present inventive conceptsis defined by the following claims, with equivalents of the claims to beincluded therein.

What is claimed is:
 1. A method for fabricating a semiconductor device, comprising: forming a first active region and a second active region; forming a gate electrode intersecting the first active region and the second active region on the first active region and the second active region; conformally forming a conductive buffer layer on the first active region, the second active region, and the gate electrode; forming a first mask pattern covering the first active region on the buffer layer; and performing a halo ion implantation process in the second active region at sides of the gate electrode using the first mask pattern.
 2. The method of claim 1, further comprising: after removing the first mask pattern, forming a second mask pattern which covers the second active region on the buffer layer; and performing the halo ion implantation process on the first active region at sides of the gate electrode using the second mask pattern.
 3. The method of claim 1, wherein the first mask pattern is a BARC
 4. The method of claim 1, wherein the buffer layer includes a TiN film or an amorphous silicon film.
 5. The method of claim 1, wherein the first active region is a region where a pull-up transistor of an SRAM is formed and the second active region is a region where a pull-down transistor of the SRAM is formed.
 6. The method of claim 1, wherein the first active region and the second active region are fin type active patterns.
 7. A method for fabricating a semiconductor device, comprising: forming a first fin type active pattern and a second fin type active pattern on a substrate, the first fin type active pattern and the second fin type active pattern being formed in a first region and a second region of the substrate, respectively; forming a first dummy gate electrode intersecting the first fin type active pattern on the first fin type active pattern and a second dummy gate electrode intersecting the second fin type active pattern on the second fin type active pattern; forming a buffer layer including a TiN film or amorphous silicon on the first and second fin type active patterns and the first and second dummy gate electrodes; forming a first mask pattern covering the first region on the buffer layer, the first mask pattern comprising a BARC; forming a first impurity region in the second fin type active pattern at sides of the second dummy gate electrode using the first mask pattern as a mask of an ion implantation process; after removing the first mask pattern, forming a second mask pattern covering the second region on the buffer layer, the second mask pattern being a BARC; and forming a second impurity region having a different conductive type from the first impurity region, in the first fin type active pattern at sides of the first dummy gate electrode using the second mask pattern as a mask of an ion implantation process.
 8. The method of claim 7, wherein the first impurity region and the second impurity region comprises halo ion implantation regions.
 9. The method of claim 7, further comprising: sequentially removing the second mask pattern and the buffer layer; forming a first source/drain at sides of the first dummy gate electrode; and forming a second source/drain at sides of the second dummy gate electrode.
 10. The method of claim 9, further comprising: forming an interlayer insulating layer which covers the first and second dummy gate electrodes and the first and second sources/drains, on the substrate; planarizing the interlayer insulating layer to expose the first dummy gate electrode and the second dummy gate electrode; removing the first dummy gate electrode and the second dummy gate electrode to form a first trench and a second trench in the interlayer insulating layer; and forming a first gate electrode which buries the first trench and a second gate electrode which buries the second trench. 